Reference is made to FIG. 1 which shows a schematic diagram of a standard six transistor (6T) static random access memory (SRAM) bitcell 10. The bitcell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true node 16 and a complement node 18. The bitcell 10 further includes two transfer (passgate) transistors 20 and 22 whose gate terminals are coupled with a wordline node and are controlled by the signal present at the wordline node (WL). Transistor 20 is source-drain connected between the true node 16 and a node associated with a true bitline (BLT). Transistor 22 is source-drain connected between the complement node 18 and a node associated with a complement bitline (BLC). The source terminals of the p-channel transistors in each inverter 12 and 14 are coupled to receive a high supply voltage (for example, VDD) at a high voltage node VH, while the source terminals of the n-channel transistors in each inverter 12 and 14 are coupled to receive a low supply voltage (for example, GND) at a low voltage node VL. The high voltage VDD at the node VH and the low voltage GND at the node VL comprise the power supply set of voltages for the cell 10.
Reference is made to FIG. 2 which shows a schematic diagram of a standard eight transistor (8T) SRAM bitcell 30 that supports decoupled read and write ports. The bitcell 30 includes two cross-coupled CMOS inverters 32 and 34, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 32 and 34 are coupled to form a latch circuit having a true node 36 and a complement node 38. The bitcell 30 further includes two transfer (passgate) transistors 40 and 42 whose gate terminals are coupled with a write wordline node and are controlled by the signal present at the write wordline node (WWL). Transistor 40 is source-drain connected between the true node 36 and a node associated with a true bitline (BLT). Transistor 42 is source-drain connected between the complement node 38 and a node associated with a complement bitline (BLC). The source terminals of the p-channel transistors in each inverter 32 and 34 are coupled to receive a high supply voltage (for example, VDD) at a high voltage node VH, while the source terminals of the n-channel transistors in each inverter 32 and 34 are coupled to receive a low supply voltage (for example, GND) at a low voltage node VL. The high voltage VDD at the node VH and the low voltage GND at the node VL comprise the power supply set of voltages for the cell 30. The bitcell 30 further includes an n-channel transistor 44 source-drain connected between the low voltage node VL and an intermediate node 46, and an n-channel transistor 48 connected between the intermediate node 46 and a read bitline (RBL). The gate terminal of transistor 44 is coupled to the complement node 38. The gate terminal of transistor 48 is coupled to a read wordline node and is controlled by the signal present at the read wordline node (RWL).
Reference is made to FIG. 3 which shows a schematic diagram of a standard ten transistor (10T) SRAM bitcell 50 that supports decoupled read and write ports. The bitcell 50 includes two cross-coupled CMOS inverters 52 and 54, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 52 and 54 are coupled to form a latch circuit having a true node 56 and a complement node 58. The bitcell 50 further includes two transfer (passgate) transistors 60 and 62 whose gate terminals are coupled with a write wordline node and are controlled by the signal present at the write wordline node (WWL). Transistor 60 is source-drain connected between the true node 56 and a node associated with a true bitline (BLT). Transistor 62 is source-drain connected between the complement node 58 and a node associated with a complement bitline (BLC). The source terminals of the p-channel transistors in each inverter 52 and 54 are coupled to receive a high supply voltage (for example, VDD) at a high voltage node VH, while the source terminals of the n-channel transistors in each inverter 52 and 54 are coupled to receive a low supply voltage (for example, GND) at a low voltage node VL. The high voltage VDD at the node VH and the low voltage GND at the node VL comprise the power supply set of voltages for the cell 50. The bitcell 50 further includes an n-channel transistor 64 source-drain connected between the low voltage node VL and an intermediate node 66, and an n-channel transistor 68 connected between the intermediate node 66 and a complement read bitline (RBLC). The gate terminal of transistor 64 is coupled to the complement node 58. The gate terminal of transistor 68 is coupled to a read wordline node and is controlled by the signal present at the read wordline node (RWL). The bitcell 50 further includes an n-channel transistor 74 source-drain connected between the low voltage node VL and an intermediate node 76, and an n-channel transistor 78 connected between the intermediate node 76 and a true read bitline (RBLT). The gate terminal of transistor 74 is coupled to the true node 56. The gate terminal of transistor 78 is coupled to a read wordline node and is controlled by the signal present at the read wordline node (RWL).
In an integrated circuit including the SRAM bitcells 10, 30 or 50, for example in an SRAM device or circuit which embeds an SRAM array, the power supply set of voltages may be received at pins of the integrated circuit, or may instead be generated on chip by a voltage regulator circuit which receives some other set of voltages from the pins of the chip. The power supply set of voltages at the nodes VH and VL are conventionally applied to the SRAM bitcell 10, 30, 50 at all times that the cell/integrated circuit is operational. It will be recognized that separate low voltage values at node VL may be provided for the sources of the n-channel MOS transistors in the inverters while separate high voltage values at node VH may be provided for the sources of the p-channel MOS transistors in the inverters.
To form an SRAM device or embedded SRAM array, a plurality of the bitcells 10, 30 or 50 are arranged in a matrix configuration to form a plurality of rows and columns. Row address decoder and column address decoder circuitry known in the art is provided and coupled to the rows and columns, respectively, of the memory matrix. The connection to the rows is made through the word lines, and the connection to the columns is made through column selection circuits coupled to the bit lines. Sense amplifier (read) circuitry, write drive circuitry and input/output circuitry is also coupled to the bit lines. The configuration of such an SRAM is well known to those skilled in the art.
There is a need in the art to improve the write time, write margin and read speed of the SRAM bitcells 10, 30, 50 operating in an SRAM device.